High performance digital-to-analog converters (DACs) utilized in applications in which high linearity is desired often use unary-weighted signals such as, for example, thermometer-coded or 1-of-n coded signals because as the resolution of a DAC increases, achieving the desired linearity becomes difficult through sizing circuit elements and layout techniques alone. Scrambling the input of a unary-weighted DAC enables utilization of different unit output elements of the DAC for a given input, resulting in improved linear response compared to a non-scrambled DAC input.
In a unary DAC system, testing for stuck-at faults in which a unary element is always ON or OFF due to manufacturing fault may include ramping the input from a minimum to a maximum in a step size of 1 and measuring the output differential non-linearity (DNL). For an N-bit DAC, there exist approximately 2N unit elements to be tested. For example, depending upon the DAC configuration details, the number of elements to be tested is either 2N or 2N−1 (i.e. 8-bit unary-weighted DAC's can have either 255 or 256 unit elements, and produce either 256 or 257 unique output values). This process for testing may take a long time for a high resolution DAC. For example, testing a 10-bit DAC in the above described manner would utilize 1024 separate measurements. The support circuitry for such testing increases proportionally to DAC resolution, which translates to area, power, design complexity, and costs.
Further, testing a digital portion of a DAC system, such as, for example, a decoder and a scrambler may be performed utilizing digital scan techniques. However including digital scanning capability into a DAC system increases the circuit complexity of the DAC system.
Improvements to testing unary DAC systems are desired.